The present disclosure relates to hybrid data transmission circuits which support a plurality of interface standards utilizing different ratios of parallel-to-serial conversion.
Low voltage differential signaling (LVDS) is used as an interface for data transmission between image processing LSIs or between an image processing LSI and a display driver in a digital television set. There are a plurality of standards for LVDS, such as one compliant to IEEE 1596.3-1996 Standard for LVDS for Scalable Coherent Interface (SCI) (hereinafter referred to as “std-LVDS”), mini-LVDS, etc. In order to increase flexibility in development of chipsets, there has been an increasing need for a so-called hybrid LVDS circuit, which supports a plurality of LVDS standards in a single LSI.
The conversion ratio of parallel-to-serial conversion and the working frequency depend on the LVDS standards. For example, the std-LVDS standard utilizes parallel-to-serial conversion of 7:1, serial data transmission at 945 Mbps, and transmission of a 135 MHz clock. Meanwhile, the mini-LVDS standard utilizes parallel-to-serial conversion of 4:1, serial data transmission at 480 Mbps, and transmission of a 240 MHz clock.
Examples of the architecture of an LVDS circuit include a single-clock architecture in which parallel-to-serial conversion is performed using a high-speed single clock, and a multiphase architecture in which parallel-to-serial conversion is performed using low-speed multiphase clocks. The single-clock architecture needs a voltage-controlled oscillator (VCO) to operate at a high-speed, and thus has a problem in that the power consumption is high. Moreover, since a parallel-to-serial conversion circuit also needs to operate at a high speed, an increase in speed is difficult to achieve. Meanwhile, the multiphase architecture allows the parallel-to-serial conversion to be performed using a plurality of clocks having phases different from one another, and accordingly low speed clocks can be used, thereby allowing the power consumption to be reduced. In addition, since the operation speed of a parallel-to-serial conversion circuit can be reduced, a speed increase can be easily achieved. Thus, in terms of power consumption and speed increase, the multiphase architecture is mainly used.
However, when such multiphase architecture is applied to a hybrid circuit—for example, parallel-to-serial conversion of an odd conversion ratio (7:1) and parallel-to-serial conversion of an even conversion ratio (4:1) are both provided, then both a PLL (phase-locked loop) circuit having a multiphase VCO for 7:1 conversion and a PLL circuit having a multiphase VCO for 4:1 conversion need to be provided. This causes an increase in the circuit area and the cost.
One solution to solve this issue is described in U.S. Pat. No. 7,228,116 (Patent Document 1). FIG. 13 illustrates a circuit configuration disclosed in Patent Document 1. The configuration of FIG. 13 includes a data transmission circuit 1000 having a parallel-to-serial conversion circuit 1001, a data transmission circuit 2000 having a parallel-to-serial conversion circuit 2001, and a PLL circuit 3000 for generating clocks respectively for the parallel-to-serial conversion circuits 1001 and 2001. The parallel-to-serial conversion circuits 1001 and 2001 have different conversion ratios, and thus the PLL circuit 3000 includes two VCO circuits 3002 and 3003 to support the two different ratios of parallel-to-serial conversion. This circuit configuration only needs to include two VCO circuits, and accordingly area reduction is easier to achieve as compared to when two PLL circuits are provided.